1. Field of the Invention
The present invention relates to a semiconductor device and, more specifically, to a semiconductor device mounting an internal power supply generating circuit.
2. Description of the Background Art
Recently, as the semiconductor devices have been developed to operate at ever lower voltages, driving of a transistor in a semiconductor device with a power supply voltage lower than the power supply voltage applied from outside of the semiconductor device has been strongly desired. The requirement of reduced power consumption of the semiconductor device and of higher reliability of the transistor are underlying factors of such trend.
In a dynamic random access memory (DRAM), it is also an important problem to ensure reliability of a dielectric film of a capacitor holding charges in a memory cell.
Upper limit of an internal power supply voltage of a semiconductor device has been made lower generation by generation due to the requirements described above, resulting in ever larger difference from the power supply voltage used in the system. Thus, a voltage down converter is provided, which is a circuit for down converting the power supply voltage used in the system to generate a stable internal power supply voltage. The voltage down converter closes a gap between the power supply voltage used in the system and the internal power supply voltage used in the semiconductor device, so as to ensure the reliability inside the semiconductor device.
FIG. 15 is a circuit diagram representing a configuration of a typical conventional voltage down converter.
Referring to FIG. 15, the voltage down converter includes a reference potential generating circuit 300 for generating a reference potential as a reference for an internal power supply potential generated in a chip, and a voltage converting unit 302 receiving a reference potential Vref generated by reference potential generating circuit 300 and generating an internal power supply potential int.Vcc.
Voltage converting unit 302 includes a differential amplifier circuit 304 comparing levels of reference potential Vref and internal power supply potential int.Vcc, and a P channel MOS transistor 306 receiving an output of differential amplifier circuit 304 at its gate, and connected between an external power supply node receiving an external power supply potential Ext.Vcc and an internal power supply node outputting the internal power supply potential int.Vcc.
Differential amplifier circuit 304 has a negative input node connected to the reference potential Vref and a positive input node receiving the internal power supply potential int.Vcc. Differential amplifier circuit 304 controls switching of P channel MOS transistor 306 to stabilize the internal power supply potential int.Vcc to the same level as the reference potential Vref.
FIG. 16 is a circuit diagram representing a configuration of reference potential generating circuit 300 of FIG. 15.
Referring to FIG. 16, reference potential generating circuit 300 includes a constant current source 312 and a resistance circuit 313 connected in series between a power supply node to which the external power supply potential Ext.Vcc is applied and the ground node. A connection node between constant current source 312 and resistance circuit 313 is an output node of reference potential generating circuit 300, from which reference potential Vref is output.
Reference potential generating circuit 300 further includes a capacitor 324 for stabilizing potential, connected between the output node outputting the reference potential Vref and the ground node.
Resistance circuit 313 includes P channel MOS transistors 314 to 322 connected in series between the output node outputting the reference potential Vref and the ground node. P channel MOS transistors 314 to 322 receive at their gates the ground potential.
Resistance circuit 313 further includes a switch circuit 326 connected in parallel with P channel MOS transistor 314, a switch circuit 328 connected in parallel with P channel MOS transistor 316, a switch circuit 330 connected in parallel with P channel MOS transistor 318, and a switch circuit 332 connected in parallel with P channel MOS transistor 320.
As a constant current applied from constant current source 212 flows against the channel resistances of P channel MOS transistors 314 to 322, reference potential Vref is determined. In order to prevent fluctuation of reference potential Vref due to the variation of channel resistances of P channel MOS transistors, switch circuits 316 to 332 include fuse elements. The configuration allows adjustment of reference potential Vref by changing the state of conduction of each fuse element. By switching the switch circuits between the conduction and non-conduction states in accordance with the setting of the fuses, tuning to 24 different values, that is, 16 values is possible.
Determination of fuse setting will be described in the following.
FIG. 17 is a circuit diagram showing detailed configuration of switch circuit 326.
Referring to FIG. 17, switch circuit 326 includes a pad 390 receiving a tuning signal TSIGn, an inverter 392 receiving and inverting the tuning signal TSIGn, an N channel MOS transistor 396 connected in series between nodes NAn and NBn, a fuse element 398, and a P channel MOS transistor 394 connected in parallel with N channel MOS transistor 396 and receiving tuning signal TSIGn.
An output of inverter 392 is applied to the gate of N channel MOS transistor 396. Node NAn is connected to the source of P channel MOS transistor 314 of FIG. 15, and node NBn is connected to the drain of P channel MOS transistor 314.
In a default state where the fuse is not blown off and the tuning signal TSIGn is at an L (low) level, nodes NAn and NBn of switch circuits 326 are conducted. When the tuning signal TSIGn is set to an H (high) level, conduction is lost between nodes NAn and NBn, and thus a state is established which is equivalent to the state where fuse element 398 is blown off.
Switch circuits 328 and 330 shown in FIG. 16 have similar structures as switch circuit 326, and therefore, description thereof is not repeated.
FIG. 18 is a circuit diagram representing a configuration of switch circuit 332 shown in FIG. 16.
Referring to FIG. 18, switch circuit 332 includes a P channel MOS transistor 402 having its gate connected to the ground node and its source coupled to the external power supply potential Ext.Vcc, an N channel MOS transistor 406 having its gate connected to the ground node and connected between node N31 and the ground node, a fuse element 404 connected between the drain of P channel MOS transistor 402 and node N31, N channel MOS transistors 420 and 422 connected in parallel between node N31 and the ground node, and an inverter 410 having an input node connected to node N31.
A signal BIAS of which level is constant is applied to the gate of N channel MOS transistor 420, and an output of inverter 410 is applied to the gate of N channel MOS transistor 422.
Switch circuit 332 further includes a pad 408 receiving the tuning signal TSIGn, an OR circuit 412 receiving the tuning signal TSIGn and an output of inverter 410, an inverter 414 receiving and inverting an output of OR circuit 412, and a P channel MOS transistor 418 and an N channel MOS transistor 416 connected in parallel between nodes NAn and NBn.
An output of OR circuit 412 is applied to the gate of N channel MOS transistor 416, and an output of inverter 414 is applied to the gate of P channel MOS transistor 418.
In the default state where tuning signal TSIGn is at the L level and fuse element 404 is not blown off, conduction is not established between nodes NAn and NBn in switch circuit 332. Node NAn of switch circuit 332 is connected to the source of P channel MOS transistor 320 of FIG. 15, and node NBn is connected to the drain of P channel MOS transistor 320.
A constant current flows through N channel MOS transistor 420 because of the potential BIAS. When fuse element 404 is blown off, the potential of node N31 attains to the L level, and in response, conduction is established between nodes NAn and NBn. When the tuning signal TSIGn is set to the H level, conduction is established between nodes NAn and NBn, attaining an equivalent state as the state where fuse 404 is blown off.
FIG. 19 is a block diagram illustrating a configuration of a conventional boosted power supply circuit generating a boosted potential provided in a semiconductor device.
Referring to FIG. 19, in the conventional semiconductor device, when the reference potential Vref to be applied to the voltage down converter is to be tuned, the boosted power supply circuit is inactivated. More specifically, a ring oscillator 332 generating fundamental clock of the boosted power supply circuit stops its operation in response to the tuning signal, so that application of a clock signal xcfx860 to a frequency division counter 336 is stopped, and input of clock signals xcfx86 and /xcfx86 to a charge pump 344 is stopped. Thus, operation of charge pump 334 is stopped.
Frequency division counter 336 divides frequency of clock signal xcfx860 output from the ring oscillator to provide a clock signal xcfx86 for the charge pump 344. A lower bit of a counter value, however, is generally not used. Such a counter is often not used while an operation related to setting of the fuses is in progress.
As described above, at the time of a test, a control signal is applied to establish a state equivalent to a state where the fuse is blown off, and internal power supply potential at that time is monitored, so that an optimal combination of fuse elements to be blown off can be found. Generally, the fuse element is blown off by a laser beam, using a test apparatus used exclusively therefor.
When such a laser trimming method is adopted, the fuse element is protected by a guard ring or the like so that polysilicon or the like blown off by the laser beam does not affect other circuitry. Therefore, it is impossible in a semiconductor device having a laser trimming type redundancy circuit to attain uniform shrink around the fuse element.
Shrink refers to use of design data of a semiconductor device designed in accordance with the design rule which is dominant presently or in the past with magnification modified to satisfy a corresponding new design rule to address development of new, more miniaturized semiconductor process. Shrink allows production of the semiconductor device with smaller chip area while making use of the design assets of the past.
As the design rule develops, the ratio of the chip area occupied by the fuse elements which cannot be shrunk attains relatively high, which presents a problem to be solved.
Further, the signal input pad provided in the semiconductor device also requires handling different from other regions at the time of shrinkage. Generally, in order to tune the reference potential Vref, signal input pads for receiving tuning signals TSIG1 to TSIG4 as inputs and a monitor pad for monitoring the reference potential Vref or the internal power supply potential int.Vcc are necessary, which means that the number of pads is disadvantageously large.
An object of the present invention is to provide a semiconductor device which can reduce the number of pads necessary for tuning the reference potential Vref, the chip area and the time necessary for tuning.
Briefly stated, the present invention provides a semiconductor device including a tuning signal generating circuit and a reference potential generating circuit. The tuning signal generating circuit outputs, in accordance with time change of a control signal of a single bit, a tuning signal having a plurality of signal bits. The reference potential generating circuit receives a first power supply potential and a second power supply potential lower than the first power supply potential, and outputs a reference potential in accordance with the tuning signal.
Therefore, an advantage of the present invention is that the number of pads necessary for tuning the reference potential Vref can be reduced and hence, the chip area of the semiconductor device can be reduced.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.